Semiconductor device with a protective security coating comprising multiple alternating metal layers

ABSTRACT

The semiconductor device comprises a substrate ( 10 ) with a first ( 1 ) and an opposed second side ( 2 ), at which first side a plurality of transistors and interconnects is present, which are covered by a protective security covering ( 16 ), which device is further provided with bond pad regions ( 14 ). The protective security covering ( 16 ) comprises a substantially non-transparent and substantially chemically inert security coating ( 16 ), and the bond pad regions ( 14 ) are accessible from the second side of the substrate ( 10 ). The semiconductor device can be suitable made with a substrate transfer technique, in which a second substrate ( 24 ) is provided at the protective security covering ( 16 ).

The invention relates to a semiconductor device comprising a substratewith a first side, at which first side a plurality of transistors andinterconnects is present, which are covered by a protective securitycovering, which device is further provided with bond pad regions.

The invention also relates to a carrier comprising a semiconductordevice.

The invention further relates to a method of manufacturing asemiconductor device provided with a substrate with a first side,comprising the steps of:

-   -   providing a structure of transistors and interconnects at the        first side of the substrate, the structure including bond pad        regions;    -   applying a protective security covering; and    -   patterning the protective security covering from the first side        so as to expose the bond pad regions.

Security issues are becoming increasingly important aspects insemiconductor design and deployment particularly as the amount and rangeof potentially sensitive commercial and/or personal information that canbe stored by, and transferred between electronic devices increases.Smart cards comprise one such form of electronic device in which it isessential to attempt to protect against invasive procedures such asattempted tampering with the integrity of the integrated circuit device,and procedures involving reverse engineering and exposure to radiation.

Security coatings for integrated circuit devices have been used in anattempt to improve the physical integrity of, for example, integratedcircuit devices found on smart cards, by seeking to restrict the mannerin which information held by the integrated circuit device can beaccessed or modified.

One such level of protection designed by Schlumberger is referred to asSishell. The process steps adopted by Schlumberger in the provision ofits Sishell protection process requires the processing of the activedevices, i.e. the integrated circuits within the smart card, tocompletion in a manner such that a passivation layer is located asrequired and the required bond pads are opened through the passivationlayer. A layer of bare silicon is then glued over the upper surface ofthe integrated circuit and the silicon layer is provided with apertures,which are located so as to correspond with the locations where the bondpad openings within the integrated circuit are found. The stackcomprising the integrated circuit, glue layer and silicon layer is thenthinned by processing of the undersurface of the silicon substrate ofthe integrated circuit so as to achieve a required total thickness. Inthis manner, the integrated circuit side of the stack also becomes verysensitive and prone to damage and breakage if an attempt is made to liftoff the silicon layer from above the passivation layer by mechanicalmeans. However, insofar as the protective silicon cover layer is etchedand patterned with regard, in particular, to the bond pad openings, suchlayer is disadvantageously prone to becoming etched and removed and thislimits its integrity of security. Also the sensitivity to breakage ofthe integrated circuit can readily be overcome by fixing the integratedcircuit to, for example, a sapphire substrate. Also, the stack structureformed is not sufficiently dense so as to prevent damage throughinfrared radiation and, somewhat further disadvantageously, silicongenerally exhibits a transparency to infrared radiation, so that theunderlying structures can then be observed.

Known process of this type are therefore disadvantageous in that thesemiconductor device formed is provided with a security coating thatonly enhances the security of the device to a disadvantageously limiteddegree.

It is therefore a first object of the invention to provide asemiconductor device of the type mentioned in the opening paragraphwhich has a substantially enhanced security.

It is a second object to provide a carrier with the semiconductor deviceof the invention.

It is a third object of the invention to provide a method ofmanufacturing a semiconductor device of the kind mentioned in theopening paragraph, which exhibits an advantage over known such methods.

The first object is realized in that the protective security coveringcomprises a substantially non-transparent and substantially chemicallyinert security coating, and that the bond pad regions are accessiblefrom the second side of the substrate.

As there is no need in the device of the invention to etch or patternthe protective security covering for bond pad access, it is possible toemploy one, or a combination of, near chemically inert material layersin the security covering. Therewith it becomes almost impossible topolish the security covering, which greatly enhances the protectionoffered.

Although it might appear at first sight that the semiconductor device ofthe invention is at its second side open to probing and to detect anystructures, this is not true or the problem can be solved. First of all,the bond pads can be protected by antiprobing means. This is notdifferent from the prior art situation. Such antiprobing means can be ofa software nature, a hardware nature or a combined hardware/softwarenature. For example, it can be prescribed that a signal should have aspecific pattern and alternatively is directly connected to a groundplane.

The bond pad regions can be accessible to the second side of thesubstrate in various manners. It is preferably that the substrate isthinned and locally etched. This option is very suitable for siliconsubstrates. After the etching of the substrate bumps can be provided atthe bond pad regions. Alternatively, the etched windows can be filledwith metal, for example by electroplating.

In the preferred case that the substrate is a silicon substrate, thesubstrate with its dense packing of transistors offers a security initself. The packing is here at its most dense in view of thetransistors, preferably field-effect transistors, and contact plugsfound therein. Any attempt to reach such structures will immediatelyresult in damage to the junctions and to any thin gate oxides such thatthe integrated circuit device will not then function. In addition, it isalmost impossible in practice to successfully probe sub-half-microndevices. Besides, in order to modify the pattern and data implemented ina semiconductor device, it are not only the individual transistors andother semiconductor elements that are vulnerable to attack, but also thecircuit as implemented in the interconnect pattern. The dense packing oftransistors effectively shields this circuit from the second side.

Nevertheless, a security layer can be provided at the second side of thesubstrate, which security layer leaves exposed the bond pad regions orany metallisation for access thereto. This option can be used withsilicon or other semiconductor substrates. It is however in particularpreferred in the case that the transistors are of the thin-film typethat are present on an insulating substrate. Such a structure will havethe advantage of flexibility, and is therefore very suitable forintegration in flexible carriers, such as banknotes, other securitypapers, labels and tags. Further on, in the case of an insulatingsubstrate with thin film transistors, the insulating substrate can be orcontain a security layer or could be replaced by a security layer afterprocessing if so desired.

In general, the protective security covering will contain a passivationlayer to protect the underlying structure from any disadvantageous orcontaminating influences of the security coating. It is further onpreferred that an adhesion layer is present between the passivationlayer and the security coating. A preferred example of such passivationlayer is a layer of TiO2, which is chemically inert, closed andnon-porous.

The security coating can contain a layer with a matrix ofaluminummetaphosphate. Such a layer that is generally filled withparticles such as TiN and TiO2 has as advantages of being chemicallyinert, non-transparent to radiation, relatively hard and brittle, anddifficult to polish. It is preferably made from a precursor material,such as Al(H2PO3), or monoaluminumphosphate. This material is convertedto aluminummetaphosphate in an anneal.

Alternatively or in addition thereto, the security coating is formed ofmultiple alternate layers, which alternate layers are sensitive todifferent etchants. Particularly preferred is a combination of alternateW and Al containing layers. The combination of such metals such as thosedefined proves to be particularly difficult to etch and polish,particularly by chemical mechanical means. This arises since Al does notetch in W etchants and vice versa. Also, when considering polishing sucha structure, it will be necessary to change from one polishing pad toanother every time each of the different layers is expected at thesurface otherwise integration of the respective polishing pads is likelyto become compromised and the pad damaged. However it should beappreciated that the basis of such a layer structure is W and then anymetal that adheres to W and does not etch in H202/NH4OH orfluorine-containing plasma. The use of Al containing layers isparticularly advantageous in allowing for ready handling and processingof the semiconductor device in an efficient manner.

In general, it will be understood that the security is most enhancedtherewith that the security coating is unpatterned. However, there maybe applications in which it is preferred to have patterning at both thefirst and the second side. Such an application arises for example withdevices, that are capacitively coupled to an antenna structure that ispresent in the carrier, which is disclosed in the non-prepublishedapplication with number EP00203298.5. In this case the capacitorelectrodes can be provided on the first side and on the second side ofthe integrated circuit, whereas there is nevertheless an adequatesecurity protection through the security coatings. A suitable securitycoating that can be patterned, is for example based on a matrix ofmonoaluminumphosphate. Patterning thereof may be done with a lift-offprocess.

The second object of a carrier with improved security is achieved inthat the carrier comprises the semiconductor device of the invention.The carrier can be a smartcard, but may further be a tag, a label, asecurity paper including a banknote or even a record carrier such as anoptical disc. As stated above, the record carrier may contain an antennastructure that is capacitively or with contact coupled to thesemiconductor device.

The third object of an improved method of manufacturing a semiconductordevice provided with a substrate with a first and second side isrealized in that it comprises the steps of:

-   -   providing a structure of transistors and interconnects at the        first side of the substrate, the structure including bond pad        regions that are defined at an interface with the substrate;    -   applying a protective security covering including at least a        substantially non-transparent and substantially chemically inert        security coating;    -   patterning the substrate from the second side so as to expose        the bond pad regions.

Processing the semiconductor device structure in this manner provesparticularly advantageous in that, since the silicon substrate iseffectively etched from underneath, there is no need to etch or patternthe protective coating for bond pad access and so it then provespossible to employ one, or a combination of, near chemically inertmaterial layers for the security coatings, for bond pad access, sincethey do not subsequently have to be patterned. Such a requirement forpatterning in the prior-art is disadvantageous.

Preferably, the substrate is a silicon substrate that is first thinned,for example by grinding or chemical-mechanical polishing and thenlocally etched. Etching means include KOH.

In a most preferred embodiment, a second substrate is provided on theprotective security covering and attached to it by means of glue. Such atechnique is also known as substrate transfer, and is per se known, forexample of U.S. Pat. No. 5,689,138. The second substrate may contain anymaterial, and is preferably providing mechanical support for thestructure. Suitable materials include glass, aluminumoxide, silicon,epoxy, and the like. Preferably the glue layer has a thickness of somemicrometers wherewith any unequalness in the surface of the protectivesecurity covering is overcome. Alternatively, an additional planarizinglayer may be provided on top of the security covering.

The invention is described further hereinafter, by way of example only,with reference to the accompanying drawings in which FIGS. 1–8 comprisecross-sectional illustrations of the formation of a semiconductor devicewith a protective security covering formed thereon. Same referencenumbers refer to like elements in the drawings. The drawings arediagrammatic and not on scale.

Turning now to the drawings, FIG. 1 illustrate an initial siliconsubstrate 10 with a first side 1 and a second side 2. The substrate 10comprises a completed integrated circuit wafer structure including apassivation layer 12 in which projected bond pad regions 14. For reasonsof clarity any interconnect layers that are present on the substrate 10have been omitted in the drawings. It is however to be understood, thatthe bond pad regions 14 are present at the interface with the siliconsubstrate 10, or such that they can be exposed from the second side 2 ofthe substrate 10. This is contarily to the location of the bond padregions in the prior art, wherein they were present in the top of theinterconnect structure, and before being exposed, only being covered bythe passivation layer 12. As will be understood by any skilled person,the bond pad regions are such defined, that there is no overlap with thetransistors on perpendicular projection of the bond pad regions on thesubstrate.

In accordance with one particular aspect of the present invention, aplurality of security coatings 16 is deposited upon the passivationlayer 12, the process of the present invention being such that there isno need to etch nor pattern the security coatings 16 and there is noneed at this stage for the bond pad regions 14 to be opened. Thepassivation layer 12 may be omitted, but is preferably present. Theplurality of security coatings forms the protective security covering.

With regard to FIG. 2, the security coatings 16 in the illustratedexample comprises a TiO2 layer 18, a coating layer 20 based onmonoAluminiumPhosphate (MAP) filled with particles of TiO2 and/or TiN,and subsequently a multi alternating layer structure 22 formed of Al andW layers respectively.

Subsequent to the coating of the substrate passivation layer structureas illustrated in FIG. 2, a substrate 24, which can be in the form of asilicon wafer substrate or a glass substrate such as AF45 is attached bymeans of a layer of glue 26 to the upper surface of the protectivecoatings 16, and as shown in FIG. 3.

As illustrated in FIGS. 3 and 4, and by means of a substrate transferprocess, the structure is then manipulated and processed in a manner soas to thin the silicon substrate 10 by action against the undersidethereof.

The underside of the structure illustrated in FIG. 4 is then manipulatedand processed by means of, for example, a KOH etch at the regions 28where the bond pads 14 are projected so as to arrive at the structure asillustrated in FIG. 5.

FIG. 6 illustrates the structure of FIG. 5 once inverted and the portion7 illustrated in FIG. 6 is shown in greater detail in FIG. 7 whichserves to illustrate a nitride layer 30 provided above the bond padopening and also part of the semiconductor circuitry 32 provided underthe thinned silicon substrate 10 which in accordance with theillustration of FIG. 7 is now oriented above the structure.

A selective etch is then conducted so as to arrive at the structure asillustrated in FIG. 8 which allows for subsequent testing and packagingof the integrated circuit device as required.

As will be appreciated particularly from FIGS. 6–8, the employment of asubstrate transfer technique in accordance with this illustratedembodiment of the present invention proves particularly advantageous inthat it allows for the ready processing of the structure in an manner soas to allow for the provision of security coatings formed ofsubstantially inert materials. Also in providing for openings to thebond pad regions through the thinned semiconductor substrate, anappropriate degree of protection due to the density of device structuresprovided therein is provided and which serves to prevent access to theunderside of the structure without fatal damage to the device.

1. A semiconductor device comprising a substrate with a first and an opposed second side, at which first side a plurality of transistors and interconnects is present, which are covered by a protective security covering, which device is further provided with bond pad regions, characterized in that the protective security covering comprises a substantially non-transparent and substantially chemically inert security coating, the security coating including at least one layer of inorganic material, and the bond pad regions are accessible from the second side of the substrate, wherein the security coating comprises, a TiO₂ layer, a coating layer based on monoAlunuinumPhosphate (MAP) filled with particles of either TiN or TiO₂; and a multi alternating layer structure formed of Al and W layers, respectively.
 2. The semiconductor device as recited in claim 1, characterized in that the bond pad regions are present on the first side of the substrate, and the substrate is a silicon substrate, that is patterned as required for access to the bond pad regions.
 3. The semiconductor device as recited in claim 1, characterized in that a security layer is present at the second side of the substrate, which security layer leaves exposed the bond pad regions or any metallisation for access thereto.
 4. The semiconductor device as recited in claim 1, characterized in that the bond pad regions are protected against probing with antiprobe means.
 5. A carrier comprising a semiconductor device, according to claim
 1. 6. The semiconductor device as recited in claim 1, wherein the security coating is is patterned.
 7. The semiconductor device as recited in claim 6, wherein the security coating is patterned to provide capacitive coupling from the semiconductor device to an antenna structure in a carrier.
 8. The semiconductor device as recited in claim 1, wherein the security coating is patterned to provide capacitive coupling from the semiconductor device to an antenna structure in a carrier.
 9. A semiconductor device comprising a substrate with a first and an opposed second side, at which first side a plurality of transistors and interconnects is present, which are covered by a protective security covering, which device is further provided with bond pad regions, characterized in that the protective security covering comprises a substantially non-transparent and substantially chemically inert security coating, the security coating including at least one layer of inorganic material, and is formed of multiple alternate layers, which alternate layers are sensitive to different etchants and the bond pad regions are accessible from the second side of the substrate, wherein the security coating comprises, a TiO₂ layer, a coating layer based on monoAluminiumPhosphate (MAP) filled with particles of either TiN or TiO₂, and a multi alternating layer structure formed of Al and W layers, respectively. 